1. Field of the Invention
The present invention relates to a display device and controller driver, more specifically, to a display device and controller driver, which are used for displaying images by using an FRC (frame rate control) technique.
2. Description of the Related Art
Recently, the circuit sizes of the display memory and the DA converter circuit integrated within an LCD controller driver tend to be increased due to the requirements of enhanced resolution and increased color depth in display devices incorporated within cell phones and other portable devices. Although a controller driver IC, especially used in a cell phone or other portable devices, is desired to have a reduced power consumption and circuit size, the increase in the circuit size of the display memory and DA converter undesirably causes the increase in the power consumption and circuit size of the controller driver.
Additionally, requirements imposed on recent display devices include superior image quality. Therefore, it is desired to reduce the image flicker in the display devices, especially in the LCD (liquid crystal display) devices.
Japanese Laid-Open Patent Application No. 2003-162272 (hereinafter, referred to as the '272 application) discloses an image processor which provides image processing that achieves image quality as high as a commonly-used image rastering technique with a reduced memory capacity. The disclosed image processor also decreases a required transmission capacity in transmitting raster image data, while suppressing image quality deterioration. In detail, the image processor generates a bit-plane-reduced image wherein the number of bit-planes thereof is reduced less than that of the original raster image. Thereafter, the image processor generates a bit-plane-increased image wherein the number of bit-planes thereof is more than that of the bit-plane-reduced image and less than that of the original raster image. The '272 application also discloses a technique for reducing the circuit sizes of the display memory and DA converter by using an FRC technique.
FIG. 8 shows an image processor disclosed in the '272 application as a sixth embodiment. The image processor, denoted by the numeral 100, includes a preceding image processing stage 104, a memory 102, an FRC latter image processing stage 109, and an image display unit 103A. The FRC latter image processing stage 109 is composed of a threshold value generator 111B, a two-bit counter 119, a carry generator 120, and a selector 113. The preceding image processing stage 104 receives from a computer a raster image 101 which represents the grayscale level of each pixel with six bits for each of red (R), green (G) and blue (B), and performs color-reduction processing on the received raster image data 101 to generate another raster image data that represents the grayscale level of each pixel with four bits for each of red (R), green (G) and blue (B). The memory 102 stores therein the raster image data received from the preceding image processing stage 104. The threshold value generator 111B generates a threshold value on the basis of the XY-coordinates of the target pixel. The two-bit counter 119 outputs a counter output value. The counter output value is cyclically updated, every when a vertical sync signal Vsync is activated. In detail, the counter output value is sequentially set to “00”, to “11”, to “01”, and to “10” in response to the vertical sync signal Vsync, and then reset to “00”. The same step is repeated thereafter. The carry generator 120 generates a carry in response to the counter output value received from the two-bit counter 119. In detail, the carry generator 120 sets the carry to “1” when the counter output value is smaller than the threshold value received from the threshold value generator 111B; otherwise, the carry generator 120 sets the carry to “0”. As thus described, the carry is generated on the basis of the threshold value in a cycle of four frames. The selector 113 is responsive to the carry received from the carry generator 120 for selectively outputting a value selected from the value obtained by adding one to the output value of the memory 102 and the output value of the memory 102, to the image display unit 103A. The image display unit 103A displays the image of the raster image data 101 with the color depth of four bits for each color, in response to the output from the selector 113.
When the threshold value generator 111B outputs the threshold value as shown in FIG. 9, a carry generator 120 sets the carry as shown in FIG. 10. The FRC latter image processing stage 109 selects the value obtained by adding one to the output value of the memory 102, when the output of the carry generator 120 is “1”. In a case of a display device in which the grayscale level of “0” indicates the darkest brightness, the brightness of the entire image is increased as the increase in the frequency in which the carry is set to the value “1”; in other words, the brightness is increases as the increase in the probability in which the carry generator 120 sets the carry to the value “1”. Therefore, the brightness of the entire image for the Vsync counter value of “3” is higher than that for the Vsync counter value of “0”, since the probability of the carry being set to “1” is 0/16 for the Vsync counter value of “0”, while the probability of the carry being set to “1” is 12/16 for the Vsync counter value of “3”, as shown in FIG. 10. In the operation, the carry is cyclically updated, and this undesirably causes the flicker in the displayed image.
Additionally, the disclosed image processor is not suitable for displaying black-and-white images. When executing an e-mail application or other applications, the display device often displays black-and-white images. The disclosed image processor implements the FRC processing even when the image data of the target pixel are all-0 or all-1. This undesirably causes the flicker in displaying black-and-white images, resulting in displaying white dots in the black background or displaying black dots in the white background.